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PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 1 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS cmos 1.3mega digital image sesnsor general description the PAS5101CS is a highly integrated cmos active-pixel image sensor that has resolution of 1280( h ) x 1024 ( v ). to have an excellent image quality, the PAS5101CS output 10-bits rgb raw data though a parallel data bus. it is available in 24-pin csp. the PAS5101CS can be programmed to set the exposu re time for different luminance condition via i2c tm serial control bus. by programming the internal register sets, it performs on-chip frame rate adjustment, offset correction dac, programmable gain control, 10-bits adc, 10-bits output companding, interpolated sub- sampling and defect compensation. key specification supply voltage 2.5v ~ 3.3v resolution 1280 ( h ) x 1024 ( v ) array diagonal 5.9mm ( ~1/3? optic ) pixel size 3.6 m x 3.6 m max. frame rate ~15 fps @ 1.3mega max. system clock up to 48mhz max. pixel clock up to 24mhz color filter rgb bayer pattern exposure time ~ frame time to line time scan mode progressive sensitivity tbd s/n ratio tbd chief ray angle 20 ~ 2 4 package type 24-pin csp features z 1.3mega resolution, ~1/3? lens. z bayer rgb color filter array. z 10-bits parallel rgb raw data output. z on-chip 10-bits pipeline a/d converter. z on-chip programmable gain amplifier ? 4-bits color gain amplifier. ? 4-bits global gain amplifier. z digital gain stage. z continuous variable frame time. z continuous variable exposure time. z i2c tm interface. z 20ma power dissipation ( 15fps / 2.5v ). z < 10ua low power-down dissipation. z window-of-interest (woi). z sub-sampling. z defect compensation. z lens shading compensation. z pin-to-pin compatible to ov9640.
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 2 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 1. pin assignment figure 1.1 shows the PAS5101CS pin diagram pin no. name type description e4 vssa gnd analog ground. d4 vdda pwr analog power, 2.5v e5 pwdn in power down (chip power down if high ). d5 vref in internal voltage reference. c5 vddd pwr nc, internal regulator 1.8v. b5 vsync out vertical synchronization signal. a5 hsync out horizontal synchronization signal. b4 pxclk out pixel clock output. a4 vddq pwr sensor vdd, 2.5v ~ 3.3v. b3 sysclk in system clock input. a3 reset in resets all registers to their default values ( chip reset if high .) b2 vssd gnd digital ground. a2 px9 out digital data out. b1 px8 out digital data out. a1 px7 out digital data out. c1 px6 out digital data out. d1 px5 out digital data out. e1 px4 out digital data out. d2 px3 out digital data out. e2 px2 out digital data out. c4 px1 out digital data out.
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 3 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 c2 px0 out digital data out. d3 scl in i2c clock. e3 sda i/o i2c data. internal pull high resister is 10k . 2. sensor array format & output timing 2.1. physical sensor array format figure 2.1 physical sensor array format 2.2. output timing 1.3mega mode ( 1288 x 1032 ) pixel readout: h_start[9:0] = 0, v_start[8:0] = 0, h_size[9:0] = 1287, v_size[8:0]= 1035, lpf[7:0] = 1035, nov_size_by4[7:0] = 63, figure 2.2 inter-line timing
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 4 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 figure 2.3 inter-frame timing figure 2.4 inter-frame timing @ dark masked
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 5 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 3. block diagram & function description 3.1. block diagram figure 3.1 shows the PAS5101CS sensor block diagram the PAS5101CS is a 1/3? cmos imaging sensor with 1280 ( h ) x 1024 ( v ) physical pixels. the active region of sensor array is 1288 ( h ) x 1032 ( v ) as shown in figure 3.1. the sensor array is cover with bayer pattern color filters and -lens. the first pixel location ( 0,0 ) is programmable in 2 direction ( x and y ) and the default value is at th e left-down side of sensor array. after a programmable exposure time, the image is sampled first with cds ( correlated double sampling ) block to improve s/n ration and reduce fixed pattern noise. three analog gain stages are implemented before signal transferred by the 10-bits a/d converter. the front gain stage ( fg ) can be programmed to fit the saturation level of sensor to the full-range input of adc. the programmable color gain st age ( cg ) is used to balance the luminance response difference between b/g/r. the global gain stage ( gg ) is programmed to adapt the gain to the image luminance. the fine gained signal will be digitized by the on-chip 10-bits a/d converter. after the image data has been digitized, further alteration to the signal can be applied before the data is output. 3.2. defect compensation the defect compensation block can de tect the possible defect pixel and replace it with average output of like-colored pixels on either side of defective pixel. there is no limitation in the capability of defect number. this function is also enable / disable by user. 3.3. companding curves the companding function is used to simulate the gamma curve and do non-linear transformation before the data is output. there are 4 curves selected by setting register compand_sel as shown in figure 3.2 and this function is also enable / disable by user.
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 6 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 figure 3.2 companding curves program by compand_enh and compand_sel 3.4. power down mode the PAS5101CS can be power down by setting register ?sw_pwrdn? or by enable pwdn pin. PAS5101CS supports two power down modes : z software power down : set register ?sw_pwrd n? = 0x01 to power down all the internal block except i2c tm . z hardware power down : pull pwdn pin to high to power down the chip. the chip will go into standby mode. 3.5. reset mode the PAS5101CS can be reset by setting ?sw_reset? or by enable reset pin. PAS5101CS supports two reset modes : z software reset : set register ?sw_reset? = 0x01 to reset all the i2c tm registers. it?s only reset the register value not reset full chip. z hardwarereset : pull reset pin to high to reset the full chip. 3.6. window-of-interest ( woi ) users are allowed to define window size as well as window location in PAS5101CS. the location of window can be anywhere in the pixel array. window size and window location is defined by register ?h_start?, ?v_start?, ?v_size? and ?h_size?; th e ?h_start? defines the starting column while ?v_start? defines the starting rom of the window; the ?h_size? define the column width of the window and ?v_size? defines the row depth of the window.
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 7 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 figure 3.3 3.7.1. output timing of woi hardware windowing vga ( 640x480 ) pixels readout ( with 4 dark lines ): h_start[9:0] = 0, v_start[8:0] = 0, h_size[9:0] = 639, v_size[8:0]= 483, lpf[7:0] = 483, nov_size_by4[7:0] = 63, figure 3.4 inter-line timing of w.o.i figure 3.5 inter-frame timing of w.o.i
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 8 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 3.7. sub-sampling PAS5101CS can be programmed to output image in vga qvga and qqvga size. in the vga sub- sampling mode, both vertical and horizontal pixels are sub-sampling at 1/2; in qvga sub-sampling mode, both vertical and horizontal pixels are sub-sampling at 1/4; while in qqvga sub-sampling mode, sub- sampling at 1/8. by programming skip_analog and skip_digital, the maximum sub-sampling rate is 1/32 ( skip_analog + skip_digital ). 3.7.1. skip_analog sub-sampling ( skip_analog ) to vga ( 640x480 ) pixels readout ( with 4 dark lines ): h_start[9:0] = 0, v_start[8:0] = 0, h_size[9:0] = 1287, v_size[8:0]= 1035, lpf[7:0] = 519, nov_size_by4[7:0] = 63, skip_analog = 1 ( sub-sampling 1/2 ) figure 3.6 valid pixel = ( h_size + 1 ) / skip_analog = 1288 / 2 = 644 valid line = (((( v_siez + 1 ) ? 4 ) / skip_analog ) + 4) = (((( 1035 + 1 ) ? 4 ) / 2 ) + 4 ) = 520 figure 3.7 inter-line timing of w.o.i
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 9 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 figure 3.8 inter-frame timing of w.o.i 3.7.2. skip_digital sub-sampling ( skip_digital ) to vga ( 640x480 ) pixels readout ( with 4 dark lines ): h_start[9:0] = 0, v_start[8:0] = 0, h_size[9:0] = 1287, v_size[8:0]= 1035, lpf[7:0] = 1036, nov_size_by4[7:0] = 63, skip_digital = 1 valid pixel = ( h_size + 1 ) / skip_digital = 1288 / 2 = 644 valid line = ( v_siez + 1 ) / skip_digital = ( 1035 + 1 ) / 2 = 518 figure 3.9 inter-line timing figure 3.10 inter-frame timing
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 10 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 4. i2c tm bus PAS5101CS supports i2c bus transfer protocol and is acting as slave device. the 7 bits unique slave address is ?1000000? and supports receivi ng / transmitting spee d up to 400khz. 4.1. i2c bus overview z only two wires sda ( serial data ) and scl ( serial clock ) carry information between the devices connected to the i2c bus. normally both sda and scl lines are open collector structure and pull high by external pull-up resistors. z only the master can initiates a transfer ( star t ), generates clock signals, and terminates a transfer ( stop ). z start and stop condition : a high to low transition of the sda line while sca is high defines a start condition. a low to high transition of the sda line while sca is high defines a stop condition. please refer to figure 4.1. z valid data : the data on the sda line must be stable during the high period of the sca clock. within each byte, msb is always transferred firs t. read / write control bit is the lsb of the first byte. please refer to figure 4.2. z both the master and slave can transm it and receive data from the bus. z acknowledge : the receiving devi ce should pull down th e sda line during high period of the scl clock line when a complete byte was transfe rred by transmitter. in the case of a master received data from a slave, the master does not generate an acknowledgm ent on the last byte to indicate the end of a master read cycle. figure 4.1 start and stop conditions figure 4.2 valid data
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 11 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 4.2. data transfer format 4.2.1. master transmits data to salve ( write cycle ) z s : start. z a : acknowledge by salve. z p : stop. z rw : the lsb of 1 st byte to decide whether current cycl e is read or write cycle. rw = 1 ? read cycle, rw = 0 ? write cycle. z subaddress : the address values of PAS5101CS internal control registers. ( please refer to PAS5101CS register description ) during write cycle, the master genera tes start condition and then places the 1 st byte data that are combined slave address ( 7 bits ) w ith a read / write control bit to sda line. after slave ( PAS5101CS ) issues acknowledgment, the master places 2 nd byte ( sub address ) data on sda line. again follow the PAS5101CS acknowledgment, the master places the 8 b its data on sda line an d transmit to PAS5101CS control register ( address was assigned by 2 nd byte ). after PAS5101CS issu e acknowledgment, the master can generate a stop condition to end of this write cycle. in the condition of multi-byte write, the PAS5101CS sub-address is automatically increment af ter each data byte tran sferred. the data and a cycles is repeat until last byte write. every co ntrol registers value inside PAS5101CS can be programming via this way. 4.2.2. slave transmits data to master ( read cycle ) z the sub-address was taken from previous write cycle. z the sub-address is automatically increment after each byte read. z am : acknowledge by master. z note there is no acknowledgment fr om master after last byte read.
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 12 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 during read cycle, the master genera tes start condition and then place the 1 st byte data that are combined slave address ( 7 bits ) with a read / write control bit to sda line. after issu e acknowledgment, 8 bits data was also placed on sda line by PAS5101CS. the 8 bits data was read from PAS5101CS internal control register that address was assigned by prev ious write cycle. follow the master acknowledgment, the PAS5101CS place the next 8 bits data ( address is increment automatically ) on sda line and then transmit to master serially. the data and am cycles is repeat until the last byte read. after last byte read, am is no longer generated by master but instead by keep sda line high. the slave ( PAS5101CS ) must releases sda line to master to generate stop condition. 4.3. i2c tm bus timing 4.4. i2c tm bus timing specification standard mode parameter symbol min. max unit scl clock frequency. f scl 10 400 khz hold time ( repeated ) start condition. after this period, the first clock pulse is generated. t hd:sta 4.0 - s low period of the scl clock. t low 4.7 - s high period of the scl clock. t high 0.75 - s set-up time for a repeated start condition. t su;sta 4.7 - s
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 13 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 data hold time. for i2c-bus device. t hd;dat 0 3.45 s data set-up time. t su;dat 250 - ns rise time of both sda and scl signals. t r 30 n.d. ns ( notel ) fall time of both sda and scl signals. t f 30 n.d. ns ( notel ) set-up time for stop condition. t su;sto 4.0 - s bus free time between a stop and start. t buf 4.7 - s capacitive load for each bus line. c b 1 15 pf noise margin at low level for each connected device. ( including hysteresis ) v nl 0.1 vdd - v noise margin at high level for each connected device. ( including hysteresis ) v nh 0.2 vdd - v note : it depends on the ?high? period time of scl.
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 14 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 5. specifications absolute maximum ratings ambient storage temperature -4 0 ~ +125 v ddd 3v v dda 3v v ddq 4v supply voltage ( with respect to ground ) all input / output voltage ( with respect to ground ) -0.3v to v ddq + 1v lead temperature, surface-mount process +23 0 esd rating, human body model 2000v dc electrical characteristics ( ta = 0 ~ 70 ) symbol parameter min. typ. max. unit type : power v dda dc supply voltage ? analog 2.4 2.5 2.6 v v ddd dc supply voltage ? digital 1.8 v v ddq dc supply voltage ? i/o 2.4 3.3 v i dd operating current ( ~ 15fps / 2.5v ) 20 ma i pwdn power down current 10 a type : in & i/o reset and system clock v ih input voltage high 0.7 x v ddq v v il input voltage low 0.3 x v ddq v c in input capacitor 10 pf type : out & i/o for px 0 : 7, pxclk, h/vsync & sda, load 10pf, 1.2 k, 2.5v v oh output voltage high 0.9 x v ddq v v ol output voltage low 0.1 x v ddq v
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 15 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 ac operating condition symbol parameter min. typ. max. unit sysclk master clock frequency 48 mhz pxclk pixel clock output frequency 24 mhz sensor characteristics parameter typ. unit sensitivity tbd v/lux-sec signal to noise ratio tbd db dynamic range tbd db operation -10 ~ +70 temperature range stable image 0 ~ +50
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 16 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 6. reference circuit schematic px0 sysclk c2 0.1uf px4 px6 jp1 conn flex 24/sm 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 21 22 23 24 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 21 22 23 24 px4 pxclk agnd px8 px9 vddq scl px8 px5 vdda px0 vsy nc reset vddq agnd scl px7 px1 sda pwdn px5 pwdn dgnd reset px1 notes: vddq is 2.5v ~ 3.3v sensor io power. vdda is 2.5v sensor analog power. c1 should close to sensor vdda and agnd. c2 should close to sensor vref and agnd. px2 agnd px9 agnd sy sclk px3 pxclk sda vdda c1 0.1uf px7 px2 agnd hsync px3 px6 PAS5101CS u1 c4 e2 d2 e1 a4 a1 b2 b1 c5 e4 d4 a3 e5 b3 b4 d3 e3 b5 a5 c2 d1 c1 a2 d5 px1 px2 px3 px4 vddq px7 vssd px8 vddd vssa vdda reset pwdn sysclk pxclk scl sda vsy nc hsync px0 px5 px6 px9 vref hsync vsy nc dgnd dgnd
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 17 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 7. package information 5585 center of sensor 101.81 top view (bumps down) 5445 center of bga 160 640 side view e d 2426 2894 c b a 281.4 2 13 center of the package (it's not same as center of bga) c d bottom view (bumps up) 800 415 e d 1107 800 1193 800 45 54 ab c b a 321
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 18 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 8. reflow profile for non lead-free
PAS5101CS specification a ll rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission . 19 p ixart ima g in g inc. e -mail: fae_service@pixart.com.tw v1.0 2005/4/27 9. lens & holder 9.1. largan 40-900l 9.2. largan 40-519c 9.3. maxemil ss-4828ga 9.4. peh-0116-03aa

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